Course: Logique combinatoire et séquentielle (2025-2026) | UDBKM

Section outline

Select section General

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General

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- Select activity Announcements
  
  Announcements Forum
Select section CH1_Boolean_Algebra_Simplifiying_Logic circuits

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CH1_Boolean_Algebra_Simplifiying_Logic circuits
- Select activity CH1_Boolean_Algebra_and simplifiying Logic circuits
  
  CH1_Boolean_Algebra_and simplifiying Logic circuits File
- Select activity CH1_Boolean_Algebra_I_
  
  CH1_Boolean_Algebra_I_ File
- Select activity CH1_Boolean_Algebra_I_11
  
  CH1_Boolean_Algebra_I_11 File
- Select activity CH1_Boolean_Algebra_and simplifiying
  
  CH1_Boolean_Algebra_and simplifiying File
Select section CH2_Binary System Operations and Representation of negative numbers

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CH2_Binary System Operations and Representation of negative numbers
- Select activity CH2_Binary System Operations and Representation of negative numbers
  
  CH2_Binary System Operations and Representation of negative numbers File
- Select activity CH2_1 Digital Concepts
  
  CH2_1 Digital Concepts File
- Select activity Ch2_Binary_Codes
  
  Ch2_Binary_Codes File
- Select activity CH2_Digital_Number_Systems_I
  
  CH2_Digital_Number_Systems_I File
- Select activity CH2_Digital_Number_Systems_II
  
  CH2_Digital_Number_Systems_II File
Select section CH3_Combinational logic Design

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CH3_Combinational logic Design
- Select activity CH3_Combinational logic Design
  
  CH3_Combinational logic Design File
- Select activity CH3_Combinational logic (Add/Soust)
  
  CH3_Combinational logic (Add/Soust) File
Select section CH4_ Binary _Decoders

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CH4_ Binary _Decoders
- Select activity CH4_ Binary Multiplier_Decoders
  
  CH4_ Binary Multiplier_Decoders File
Select section CH5_ Multiplexers, Demultiplexers

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CH5_ Multiplexers, Demultiplexers
- Select activity CH5_ Multiplexers, Demultiplexers
  
  CH5_ Multiplexers, Demultiplexers File
Select section CH6_ Latches and Flip-Flops

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CH6_ Latches and Flip-Flops
- Select activity CH6_ Latches and Flip-Flops
  
  CH6_ Latches and Flip-Flops File
- Select activity CH6_ Sequential Circuits Design
  
  CH6_ Sequential Circuits Design File
- Select activity CH6_Analysis_of_Clocked_Sequential_Circuits
  
  CH6_Analysis_of_Clocked_Sequential_Circuits File
- Select activity CH6_Analysis_of_Clocked_Sequential
  
  CH6_Analysis_of_Clocked_Sequential File
Select section CH7_Design_of_Counter_I&II

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CH7_Design_of_Counter_I&II
- Select activity CH7_Design_of_Counter_I
  
  CH7_Design_of_Counter_I File
- Select activity CH7_Design_of_Counter_II
  
  CH7_Design_of_Counter_II File
Select section CH8_Registers

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CH8_Registers
- Select activity CH8_Design_of_Registers
  
  CH8_Design_of_Registers File